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Design and analysis of tunnel fet for low power cmos circuit applications

Tejabhai Vaghela Hardik

Design and analysis of tunnel fet for low power cmos circuit applications Tejabhai Vaghela Hardik - Dr.B.R.Amb - Jalandhar Dr.B.R.Ambedkar National Institute of T 2015 - xi 74p

Dewey Class. No.: 621.38 / TE-D

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